As NAND flash memory continues to be scaled down, reliability of flash memory continues to decrease. Conventional RAID (redundant array of independent drives)-like technology selects a page of the same page number in a number of memory blocks from different dies to form a super-page (S-page). Part of the S-page is user data and part of the S-page structure is parity data, which is calculated from the user-data to protect the user data. By leveraging error rate variations of different dies, the worst die can be largely protected if the whole physical flash page on the worst die fails to be corrected. A potential problem with the conventional technique is that the physical flash pages taken from different dies to form the S-page are in the same relative location inside the respective blocks. Because the “sub-pages” of a conventional S-page are in the same location inside the respective blocks, the physical layout architecture is the same and programming order is also the same. Thus, the error rate of different sub-pages in different dies can still have some correlations. In particular, the sub-pages may suffer from the same program interference and the same circuit level noise due to the same design layout architecture. For example, error rates for border pages, even/odd pages, and least significant bit/most significant bit (LSB/MSB) pages are different, which could cause the codeword failure rate to be different.
It would be desirable to have a method and/or apparatus for distributing user data and error correction data over different page types by leveraging error rate variations.